A CMOS Baseline Holder (BLH) for Readout ASICs

As a result of a cooperation between Brookhaven National Laboratory and eV Products a generation of high performance readout ASICs was developed. One of the novel circuit solutions implemented in the ASICs is the baseline holder (BLH), a system which provides setting and stabilization of the output baseline both at low frequency and at high rate operation. The BLH is conceptually different from the baseline restorer (BLR). With a output peaking voltage 2V (10fC), a peaking time 400ns and a rate 500kHz, an asymptotic shift of the baseline < 8mV was measured.